module top_module (
    input clk,
    input areset,
    input x,
    output z
); 

    reg [1:0]   state;
    reg [1:0]   nstate;
    parameter 
    idle = 2'b00,
    s1   = 2'b01,
    s2   = 2'b10;
    always@(posedge clk or posedge areset)begin
        if(areset)
            state <= idle;
        else
            state <= nstate;
    end
    always@(*)begin
        nstate = idle;
        case(state)
            idle:nstate = x? s1:idle;
            s1  :nstate = s2;
            s2  :nstate = s2;
            default:nstate = idle;
        endcase
    end
    always@(posedge clk or posedge areset)begin
        if(areset)
            z <= 1'b0;
        else
            case(nstate)
                idle:z <= 1'b0;
                s1  :z <= 1'b1;
                s2  :z <= ~x;
            endcase
    end

endmodule
